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| Issue X-1 CM1231 Two-Channel PicoGuard XPTM ESD Clamp Protection Array Features * * * * * * * * Two channels of ESD protection Exceeds ESD protection to IEC61000-4-2 Level 4: * 12kV contact discharge (OUT pins) Two-stage matched clamp architecture Matching-of-series resistor (R) of 10m typical Flow-through routing for high-speed signal integrity Differential channel input capacitance matching of 0.02pF typical. Improved powered ASIC latchup protection Dramatic improvement in ESD protection vs. best in class single-stage diode arrays * 40% reduction in peak clamping voltage * 40% reduction in peak residual current Withstands over 1000 ESD strikes* Available in a SOT23-6 package Product Description The CM1231 is a member of the XtremeESDTM product family and is specifically designed for next generation deep submicron ASIC protection. These devices are ideal for protecting systems with high data and clock rates and for circuits requiring low capacitive loading such as USB 2.0. The CM1231 incorporates the PicoGuard XPTM dual stage ESD architecture which offers dramatically higher system level ESD protection compared with traditional single clamp designs. In addition, the CM1231 provides a controlled filter roll-off for even greater spurious EMI suppression and signal integrity. The CM1231 protects against ESD pulses up to 12kV contact on the "OUT" pins per the IEC 61000-4-2 standard. The device also features easily routed "pass-through" differential pinouts in a 6-lead SOT23 package. * * Applications * * USB devices data port protection General high-speed data line ESD protection Electrical Schematic VP VP CM1231 Positive Supply Rail VCC AOUT 1 AIN Circuitry Under Protection Connector BOUT 1 BIN VN VN Ground Rail *Standard test condition is IEC61000-4-2 level 4 test circuit with each (AOUT/BOUT) pin subjected to 12kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. (c) 2007 California Micro Devices Corp. All rights reserved. 12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 1 Issue X-1 CM1231 Single and Dual Clamp ESD Protection The following sections describe the standard single clamp ESD protection device and the dual clamp ESD protection architecture of the CM1231. Single Clamp ESD Protection Conceptually, an ESD protection device performs the following actions upon a strike of ESD discharge into the protected ASIC (see Figure 1). 1. When an ESD potential is applied to the system under test (contact or air-discharge), Kirchoff's Current Law (KCL) dictates that the Electrical Overstress (EOS) currents will immediately divide throughout the circuit, based on the dynamic impedance of each path. 2. Ideally, the classic shunt ESD clamp will switch within 1ns to a low-impedance path and return the majority of the EOS current to the chassis shield/ reference ground. In actuality, if the ESD component's response time (tCLAMP) is slower than the ASIC it is protecting, or if the Dynamic Resistance (RDYN) is not significantly lower than the ASIC's I/O cell circuitry, then the ASIC will have to absorb a large amount of the EOS energy, and may be more likely to fail. 3. Subsequent to the ESD/EOS event, both devices must immediately return to their original specifications, ready for an additional strike. Any deterioration in parasitics or clamping capability should be considered a failure, as it can affect signal integrity or subsequent protection capability (this is known as "multi-strike" capability.) ESD Strike ESD ESD Protection PROTECTION Device DEVICE I /O Connector ASIC I SHUNT IRESIDUAL Figure 1. Single Clamp ESD Protection Block Diagram Dual Clamp ESD Protection In the CM1231 dual clamp PicoGuard XPTM architecture, the first stage begins clamping immediately, as it does in the single clamp case. The dramatically reduced IRES current from stage one passes through the 1 series element and then gradually feeds into the stage two ESD device (see Figure 2). The series inductive and resistive elements further limit the current into the second stage, and greatly attenuate the resultant peak incident pulse presented at the ASIC side of the device. This disconnection between the outside node and the inside ASIC node allows the stage one clamps to turn on and remain in the shunt mode before the ASIC begins to shunt the reduced residual pulse. This gives the advantage to the ESD component in the current division equation, and dramatically reduces the residual energy that the ASIC must dissipate. (c) 2007 California Micro Devices Corp. All rights reserved. I/O Connector ESD Strike 1 ESD Protection Stage 1 ESD Protection Stage 2 ASIC ASIC DUT I SHUNT1 I SHUNT2 I RESIDUAL Figure 2. Dual Clamp ESD Protection Block Diagram 2 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07 Issue X-1 CM1231 CM1231 Architecture Overview The PicoGuard XPTM two-stage per channel matched clamp architecture with isolated clamp rails features a series element to radically reduce the residual ESD current (IRES) that enters the ASIC under protection (see Figure 3). From stage 1 to stage 2, the signal lines go through matched dual 1 resistors. The function of the series element (dual 1 resistors for the CM1231) is to optimize the operation of the stage two diodes to reduce the final IRES current to a minimum while maintaining an acceptable insertion impedance that is negligible for the associated signaling levels. Each stage consists of a traditional low-cap Dual Rail Clamp structure which steer the positive or negative ESD current pulse to either the positive (VP) or negative (VN) supply rail. A zener diode is embedded between VP and VN, offering two advantages. First, it protects the VCC rail against ESD strikes. Second, it eliminates the need for an additional bypass capacitor to shunt the positive ESD strikes to ground. The CM1231 therefore replaces as many as 7 discrete components, while taking advantage of precision internal component matching for improved signal integrity, which is not otherwise possible with discrete components at the system level. Advantages of the CM1231 Dual Stage ESD Protection Architecture Figure 4 illustrates a single stage ESD protection device. The inductor element represents the parasitic inductance arising from the bond wire and the PCB trace leading to the ESD protection diodes. Connector ASIC Bond Wire Inductance ESD Stage Figure 4. Single Stage ESD Protection Model Figure 5 illustrates one of the two CM1231 channels. Similarly, the inductor elements represent the parasitic inductance arising from the bond wire and PCB traces leading to the ESD protection diodes as well. VP Positive Supply Rail VCC Bond Wire Inductance Series Element Bond Wire Inductance Connector ASIC 1 I ESD IRESIDUAL Circuitry Under Protection 1st Stage 2nd Stage VN Ground Rail Figure 3. CM1231 Block Diagram (IESD Flow During a Positive Strike) (c) 2007 California Micro Devices Corp. All rights reserved. 12/17/07 Figure 5. CM1231 Dual Stage ESD Protection Model 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 3 Issue X-1 CM1231 CM1231 Inductor Elements In the CM1231 dual stage PicoGuard XP architecture, the inductor elements and ESD protection diodes interact differently compared to the single stage model. In the single stage model, the inductive element presents high impedance at high frequency, i.e. during an ESD strike. The impedance increases the resistance of the conduction path leading to the ESD protection element. This limits the speed that the ESD pulse can discharge through the single stage protection element. In the PicoGuard XPTM architecture, the inductance elements are in series to the conduction path leading to the protected device. The elements actually help to limit the current and voltage striking the protected device. TM The reactance of the series and the inductor elements in the second stage forces more of the ESD strike current to be shunted through the first stage. At the same time the voltage drop across series element helps to lower the clamping voltage at the protected terminal. The inductor elements also tune the impedance of the stage by cancelling the capacitive load presented by the ESD diodes to the signal line. This improves the signal integrity and makes the ESD protection stages more transparent to the high bandwidth data signals passing through the channel. The innovative PicoGuard XP architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the ESD current strike to the protected device and also improves the signal integrity of the system by balancing the capacitive loading effects of the ESD diodes. Graphical Comparison and Test Setup The following graphs (see Figure 6, Figure 7, and Figure 8) show that the CM1231 (dual stage ESD protector) lowers the peak voltage and clamping voltage by 40% across a wide range of loading conditions in comparison to a standard single stage device. This data was derived using the test setups shown in Figure 9 and Figure 10. Normalized Vpeak 1 0.8 V oltage V o lt a g e 1 0.8 Normalized Vclamp Initial (0-50ns) 0.6 0.4 0.2 0 0 5 10 15 RDUP() 20 25 Single Stage ESD Device CM1231 0.6 0.4 0.2 0 0 5 10 15 RDUP () 20 25 Single Stage ESD Device CM1231 Figure 6. IEC 61000-4-2 Vpeak vs. Loading (RDUP*) Figure 7. IEC 61000-4-2 Vclamp vs. Loading (RDUP*) * RDUP indicates the amount of Resistance (load) supplied to the Device Under Protection (DUP) through a variable resistor. (c) 2007 California Micro Devices Corp. All rights reserved. 4 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07 Issue X-1 CM1231 IRES 12 10 Current (A) 8 6 4 2 0 0 5 10 15 RDUP() 20 25 Single Stage ESD Device CM1231 Figure 8. IEC 61000-4-2 IRES (Residual ESD Peak Current) vs. Loading (RDUP) IEC 6100-4-2 Test Standards Voltage Probe IEC 6100-4-2 Test Standards CM1231 Device Under Protection (DUP) Voltage Probe Single Stage ESD Device Device Under Protection (DUP) RVARIABLE R VARIABLE IRESIDUAL IRESIDUAL Current Probe Current Probe Figure 9. Single Stage ESD Device Test Setup Figure 10. CM1231 Test Setup (c) 2007 California Micro Devices Corp. All rights reserved. 12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 5 Issue X-1 CM1231 PACKAGE / PINOUT DIAGRAMS BOUT 6 VP 5 BIN 4 D312 1 2 3 AOUT Note: 1) This drawing is not to scale. VN AIN PIN DESCRIPTIONS PIN 1 2 3 4 5 6 PIN NAME AOUT VN AIN BIN VP BOUT PIN DESCRIPTION Bidirectional clamp to Connector (Outside the system) Ground return to Shield Bidirectional clamp to ASIC (Inside the system) Bidirectional clamp to ASIC (Inside the system) Bias voltage (optional) Bidirectional clamp to Connector (Outside the system) NOTES Ordering Information PART NUMBERING INFORMATION PIN 6 PACKAGE SOT23-6 LEAD-FREE FINISH CM1231-02SO Part Marking D312 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER Operating Supply Voltage (VP) Diode Forward DC Current (AOUT/BOUT Side) Continuous Current through Signal Pins (IN to OUT) 1000 hours Operating Temperature Range Storage Temperature Range DC Voltage at any channel input Package Power Rating (SOT23-6) RATING 6.0 8.0 125 -40 to +85 -65 to +150 (VN - 0.5) to (VP + 0.5) 225 UNITS V mA mA C C V mW Note 1: Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (c) 2007 California Micro Devices Corp. All rights reserved. 6 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07 Issue X-1 CM1231 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER VP ICC5 VF Operating Supply Voltage Operating Supply Current Diode Forward Voltage Top Diode Bottom Diode ESD Protection, Contact Discharge per IEC 61000-4-2 Standard OUT-to-VN Contact IN-to-VN Contact IRES Residual ESD Peak Current on RDUP (Resistance of Device Under Protection) Channel Clamp Voltage Positive Transients Negative Transients Dynamic Resistance Positive Transients Negative Transients OUT Capacitance IEC 61000-4-2 8kV; RDUP = 5, TA = 25C; Note 2 IPP = 1A, TA = 25C, tP = 8/20s, Zap at OUT, Measure at IN; Note 2 IPP = 1A, TA = 25C, tP = 8/20s, Zap at OUT, Measure at IN; Note 2 f=1 MHz, VP=5.0V, VIN=2.5V, VOSC=30mV; Note 2, 3 f=1 MHz, VP=5.0V, VIN=2.5V, VOSC=30mV Note 2 Note 2 Note 2 VP = 5V IF = 8mA, TA = 25C; Note 2 TA = 25C; Note 2 0.60 0.60 0.80 0.80 CONDITIONS MIN TYP 5 MAX 5.5 1 0.95 0.95 UNITS V A V V VESD 12 4 2.3 kV kV A VCL +9 -1.4 0.4 0.3 1.5 V V pF RDYN COUT COUT RS Channel to Channel Capacitance Match 0.02 pF Series Resistance Channel to Channel Resistance Match 1 10 30 m RS Note 1: All parameters specified at TA = -40C to +85C unless otherwise noted. Note 2: This parameter is guaranteed by design and verified by device characterization Note 3: Capacitance measured from OUT to VN with IN floating. (c) 2007 California Micro Devices Corp. All rights reserved. 12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 7 Issue X-1 CM1231 Performance Information Clamping Voltage vs . Peak Current 13.5 13 Clam ping Voltage (V) 12.5 12 11.5 11 10.5 10 9.5 9 1 2 3 4 5 IEC61000-4-5 8/20uS Peak Current (A) 0.0 0 1 2 3 4 5 Bias Voltage (V) 2.5 OUT-to-VN Capacitance, IN Floating, Vp=5V OUT-to-Vn Capacitance, IN Floating, VP=5V Zap at OUT; Measure at OUT Capacitance (pF) 2.0 Zap at OUT; Measure at IN 1.5 1.0 0.5 Figure 11. Clamping Voltage vs. Peak Current Figure 12. Capacitance vs. Bias Voltage Typical Filter Performance (nominal conditions unless specified otherwise, 0V DC bias, 50 environment) 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB -7 dB -8 dB -9 dB -10 dB 3 10 100 FREQUENCY (MHz) 1000 2000 6000 Figure 13. Typical Single-Ended S21 Plot (1dB/div, 3MHz to 6GHz) (c) 2007 California Micro Devices Corp. All rights reserved. 8 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07 Issue X-1 CM1231 CM1231 Application and Guidelines The CM1231 has an integrated zener diode between VP and VN (for each of the two stages). This greatly reduces the effect of supply rail inductance L2 on VCL by clamping VP at the breakdown voltage of the zener diode. However, for the lowest possible VCL, especially when VP is biased at a voltage significantly below the zener breakdown voltage, it is recommended that a 0.22F ceramic chip capacitor be connected between VP and the ground plane. With the CM1231, this additional bypass capacitor is generally not required. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Figure 14. Typical Layout with Optional VP Cap Footprint Additional Information See also California Micro Devices Application Note AP-209, "Design Considerations for ESD Protection," in the Applications section at www.calmicro.com. (c) 2007 California Micro Devices Corp. All rights reserved. 12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 9 Issue X-1 CM1231 Mechanical Details SOT23-6 Mechanical Specifications, 6 pin The CM1231 is supplied in a 6-pin SOT23 package. Dimensions are presented below. Mechanical Package Diagrams TOP VIEW PACKAGE DIMENSIONS Package JEDEC No. Pins/Leads Dimensions A A1 b c D E E1 e e1 L L1 # per tape and reel Millimeters Min -0.00 0.30 0.08 2.75 2.60 1.45 Max 1.45 0.15 0.50 0.22 3.05 3.00 1.75 Min -0.0000 0.0118 0.0031 0.1083 0.1024 0.0571 SOT23-6 MO-178 (Var. AB) 6 Inches Max 1 6 e1 5 e 4 Pin 1 Marking 2 3 E1 E 0.0571 0.0059 0.0197 0.0087 0.1201 0.1181 0.0689 A SIDE VIEW D b 0.95 BSC 1.90 BSC 0.30 0.60 0.60 REF 0.0374 BSC 0.0748 BSC 0.0118 0.0236 END VIEW A1 0.0236REF 3000 pieces Controlling dimension: millimeters c L1 L Dimensions for SOT23-6 Package (c) 2007 California Micro Devices Corp. All rights reserved. 10 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07 Issue X-1 CM1231 Tape and Reel Specifications PART NUMBER CM1231 PACKAGE SIZE (mm) 3.05 X 3.00 X 1.45 POCKET SIZE (mm) B0 X A0 X K0 3.20 X 3.20 X 1.40 TAPE WIDTH W 8mm REEL DIAMETER 178mm (7") QTY PER REEL 3000 P0 4mm P1 4mm Po Top Cover Tape 10 Pitches Cumulative Tolerance On Tape 0.2 mm Ao W Bo Ko For Tape Feeder Reference Only including Draft. Concentric Around B. Embossment P1 User Direction of Feed Center Lines of Cavity Figure 15. Tape and Reel Specifications (c) 2007 California Micro Devices Corp. All rights reserved. 12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 11 |
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